Theorem. (t15_power)
∀v1_xboole_0 : setprop, ∀m1_subset_1 : setsetprop, ∀k1_zfmisc_1 : setset, ∀k2_xcmplx_0 : setsetset, ∀esk5_2 : setsetset, ∀v1_abian : setprop, ∀np__2 : set, ∀v1_int_1 : setprop, ∀k6_xcmplx_0 : setsetset, ∀v3_xxreal_0 : setprop, ∀esk26_1 : setset, ∀r1_tarski : setsetprop, ∀v1_rat_1 : setprop, ∀v5_membered : setprop, ∀v3_membered : setprop, ∀v1_membered : setprop, ∀v1_xxreal_0 : setprop, ∀esk2_0 : set, ∀v7_membered : setprop, ∀v1_zfmisc_1 : setprop, ∀esk20_0 : set, ∀esk14_0 : set, ∀esk7_0 : set, ∀esk23_0 : set, ∀esk6_0 : set, ∀esk17_0 : set, ∀esk21_0 : set, ∀esk24_0 : set, ∀esk12_0 : set, ∀esk15_0 : set, ∀esk10_0 : set, ∀esk11_0 : set, ∀esk19_0 : set, ∀esk9_0 : set, ∀esk25_0 : set, ∀esk22_0 : set, ∀esk18_0 : set, ∀k4_ordinal1 : set, ∀esk8_0 : set, ∀esk4_1 : setset, ∀esk13_0 : set, ∀esk16_0 : set, ∀v1_finset_1 : setprop, ∀np__0 : set, ∀k1_xboole_0 : set, ∀v3_ordinal1 : setprop, ∀esk1_0 : set, ∀esk3_0 : set, ∀v2_setfam_1 : setprop, ∀v6_membered : setprop, ∀v2_membered : setprop, ∀v4_membered : setprop, ∀r2_hidden : setsetprop, ∀v2_xxreal_0 : setprop, ∀k4_xcmplx_0 : setset, ∀k1_power : setsetset, ∀v7_ordinal1 : setprop, ∀v1_xcmplx_0 : setprop, ∀v1_xreal_0 : setprop, ∀np__1 : set, ∀k1_numbers : set, ∀k5_numbers : set, ∀m2_subset_1 : setsetsetprop, ∀r1_xxreal_0 : setsetprop, ∀k6_numbers : set, ∀k4_nat_1 : setsetset, ∀k2_nat_1 : setsetset, ∀k1_newton : setsetset, ∀k3_xcmplx_0 : setsetset, ∀k2_prepower : setsetset, (∀X2 X3 X1, ((k3_xcmplx_0 (k2_prepower X2 X1) (k2_prepower X3 X1)) = (k2_prepower (k4_nat_1 X2 X3) (k1_newton X1 (k2_nat_1 X2 X3)))False)v1_xreal_0 X1r1_xxreal_0 k6_numbers X1r1_xxreal_0 np__1 X3r1_xxreal_0 np__1 X2m2_subset_1 X3 k1_numbers k5_numbersm2_subset_1 X2 k1_numbers k5_numbersFalse)(∀X1 X3 X2, (v1_xboole_0 X2False)(v1_xboole_0 X1False)(m1_subset_1 X3 X1False)m2_subset_1 X3 X1 X2m1_subset_1 X2 (k1_zfmisc_1 X1)False)(∀X2 X1 X3, (v1_xboole_0 X3False)(v1_xboole_0 X2False)(m1_subset_1 X1 X3False)m2_subset_1 X1 X2 X3m1_subset_1 X3 (k1_zfmisc_1 X2)False)(∀X2 X1 X3, (r1_xxreal_0 X1 X3False)v1_xreal_0 X3v1_xreal_0 X2v1_xreal_0 X1r1_xxreal_0 (k2_xcmplx_0 X1 X2) (k2_xcmplx_0 X3 X2)False)(∀X1 X2 X3, ((k2_xcmplx_0 (k3_xcmplx_0 X1 X3) (k3_xcmplx_0 X2 X3)) = (k3_xcmplx_0 (k2_xcmplx_0 X1 X2) X3)False)v1_xcmplx_0 X3v1_xcmplx_0 X2v1_xcmplx_0 X1False)(∀X1 X2, (v1_xboole_0 X2False)(v1_xboole_0 X1False)(m2_subset_1 (esk5_2 X1 X2) X1 X2False)m1_subset_1 X2 (k1_zfmisc_1 X1)False)(∀X2 X1 X3, (v1_xboole_0 X3False)(v1_xboole_0 X2False)(m2_subset_1 X1 X3 X2False)m1_subset_1 X1 X2m1_subset_1 X2 (k1_zfmisc_1 X3)False)(∀X2 X1 X3, (r1_xxreal_0 (k2_xcmplx_0 X1 X3) (k2_xcmplx_0 X2 X3)False)v1_xreal_0 X3v1_xreal_0 X2v1_xreal_0 X1r1_xxreal_0 X1 X2False)(∀X2 X1, (m2_subset_1 (k2_nat_1 X1 X2) k1_numbers k5_numbersFalse)v7_ordinal1 X2m1_subset_1 X1 k5_numbersFalse)(∀X2 X1, (m2_subset_1 (k4_nat_1 X1 X2) k1_numbers k5_numbersFalse)v7_ordinal1 X2m1_subset_1 X1 k5_numbersFalse)(∀X1 X2 X3, ((k2_xcmplx_0 (k2_xcmplx_0 X1 X2) X3) = (k2_xcmplx_0 X1 (k2_xcmplx_0 X2 X3))False)v1_xcmplx_0 X3v1_xcmplx_0 X2v1_xcmplx_0 X1False)(∀X1 X2 X3, ((k3_xcmplx_0 (k3_xcmplx_0 X1 X2) X3) = (k3_xcmplx_0 X1 (k3_xcmplx_0 X2 X3))False)v1_xcmplx_0 X3v1_xcmplx_0 X2v1_xcmplx_0 X1False)(∀X1 X2, (r1_xxreal_0 np__1 (k3_xcmplx_0 X1 X2)False)v1_xreal_0 X2v1_xreal_0 X1r1_xxreal_0 np__1 X2r1_xxreal_0 np__1 X1False)(∀X1 X2, X2 = (k2_nat_1 (k4_nat_1 np__2 X1) np__1)v1_abian X2v7_ordinal1 X2m1_subset_1 X1 k5_numbersFalse)(∀X1 X2, ((k4_xcmplx_0 (k2_prepower X2 (k4_xcmplx_0 X1))) = (k1_power X2 X1)False)(v1_abian X2False)(r1_xxreal_0 k6_numbers X1False)v1_xreal_0 X1v7_ordinal1 X2False)(∀X2 X1, (r1_xxreal_0 k6_numbers (k1_newton X1 X2)False)v1_xreal_0 X1m1_subset_1 X2 k5_numbersr1_xxreal_0 k6_numbers X1False)(∀X2 X1, ((k2_prepower X2 X1) = (k1_power X2 X1)False)v1_xreal_0 X1v7_ordinal1 X2r1_xxreal_0 k6_numbers X1r1_xxreal_0 np__1 X2False)(∀X1 X2, (v1_abian X2False)v1_abian X1v1_int_1 X2v1_int_1 X1v1_abian (k6_xcmplx_0 X1 X2)False)(∀X1 X2, (v1_abian X2False)v1_abian X1v1_int_1 X2v1_int_1 X1v1_abian (k6_xcmplx_0 X2 X1)False)(∀X1 X2, (v1_abian X2False)v1_abian X1v1_int_1 X2v1_int_1 X1v1_abian (k2_xcmplx_0 X1 X2)False)(∀X1 X2, (v1_abian X2False)v1_abian X1v1_int_1 X2v1_int_1 X1v1_abian (k2_xcmplx_0 X2 X1)False)(∀X2 X1, (r1_xxreal_0 k6_numbers (k1_newton X2 X1)False)v1_xreal_0 X2v1_abian X1m1_subset_1 X1 k5_numbersFalse)(∀X1 X2, (v2_xxreal_0 X2False)(v2_xxreal_0 X1False)v1_xreal_0 X2v1_xreal_0 X1v2_xxreal_0 (k2_xcmplx_0 X1 X2)False)(∀X1 X2, (v2_xxreal_0 X2False)(v2_xxreal_0 X1False)v1_xreal_0 X2v1_xreal_0 X1v3_xxreal_0 (k3_xcmplx_0 X1 X2)False)(∀X2 X1, (v3_xxreal_0 X1False)(v2_xxreal_0 X2False)v1_xreal_0 X2v1_xreal_0 X1v2_xxreal_0 (k6_xcmplx_0 X2 X1)False)(∀X2 X1, (v3_xxreal_0 X1False)(v2_xxreal_0 X2False)v1_xreal_0 X2v1_xreal_0 X1v3_xxreal_0 (k6_xcmplx_0 X1 X2)False)(∀X1 X2, (v3_xxreal_0 X2False)(v2_xxreal_0 X1False)v1_xreal_0 X2v1_xreal_0 X1v2_xxreal_0 (k3_xcmplx_0 X1 X2)False)(∀X1 X2, (v3_xxreal_0 X2False)(v2_xxreal_0 X1False)v1_xreal_0 X2v1_xreal_0 X1v2_xxreal_0 (k3_xcmplx_0 X2 X1)False)(∀X1 X2, (v3_xxreal_0 X2False)(v3_xxreal_0 X1False)v1_xreal_0 X2v1_xreal_0 X1v3_xxreal_0 (k2_xcmplx_0 X1 X2)False)(∀X1 X2, (v3_xxreal_0 X2False)(v3_xxreal_0 X1False)v1_xreal_0 X2v1_xreal_0 X1v3_xxreal_0 (k3_xcmplx_0 X1 X2)False)(∀X1 X2, (v1_abian X2False)(v1_abian X1False)v1_int_1 X2v1_int_1 X1v1_abian (k3_xcmplx_0 X1 X2)False)(∀X2 X1, ((k2_xcmplx_0 (k4_xcmplx_0 X1) (k4_xcmplx_0 X2)) = (k4_xcmplx_0 (k2_xcmplx_0 X1 X2))False)v1_xcmplx_0 X2v1_xcmplx_0 X1False)(∀X2 X1 X3, (m1_subset_1 X1 X3False)r2_hidden X1 X2m1_subset_1 X2 (k1_zfmisc_1 X3)False)(∀X1 X2, ((k1_newton (k4_xcmplx_0 X1) X2) = (k1_newton X1 X2)False)v1_xreal_0 X1v1_abian X2m1_subset_1 X2 k5_numbersFalse)(∀X1 X2, (v1_xboole_0 X2False)v7_ordinal1 X2v7_ordinal1 X1v1_xboole_0 (k2_xcmplx_0 X1 X2)False)(∀X1 X2, (v1_xboole_0 X2False)v7_ordinal1 X2v7_ordinal1 X1v1_xboole_0 (k2_xcmplx_0 X2 X1)False)(∀X2 X1 X3, v1_xboole_0 X3r2_hidden X1 X2m1_subset_1 X2 (k1_zfmisc_1 X3)False)(∀X1, ((k2_nat_1 (k4_nat_1 np__2 (esk26_1 X1)) np__1) = X1False)(v1_abian X1False)v7_ordinal1 X1False)(∀X1 X2, (v1_abian (k2_xcmplx_0 X1 X2)False)v1_abian X2v1_abian X1v1_int_1 X2v1_int_1 X1False)(∀X1, v1_abian X1v1_int_1 X1v1_abian (k6_xcmplx_0 X1 np__1)False)(∀X1, v1_abian X1v1_int_1 X1v1_abian (k2_xcmplx_0 X1 np__1)False)(∀X1 X2, (v2_xxreal_0 X2False)(v2_xxreal_0 (k6_xcmplx_0 X1 X2)False)v1_xreal_0 X2v1_xreal_0 X1v2_xxreal_0 X1False)(∀X1 X2, (v2_xxreal_0 X2False)(v3_xxreal_0 (k6_xcmplx_0 X2 X1)False)v1_xreal_0 X2v1_xreal_0 X1v2_xxreal_0 X1False)(∀X1 X2, (v2_xxreal_0 X2False)(v3_xxreal_0 (k2_xcmplx_0 X1 X2)False)v1_xreal_0 X2v1_xreal_0 X1v3_xxreal_0 X1False)(∀X1 X2, (v2_xxreal_0 X2False)(v3_xxreal_0 (k2_xcmplx_0 X2 X1)False)v1_xreal_0 X2v1_xreal_0 X1v3_xxreal_0 X1False)(∀X1 X2, (v3_xxreal_0 X2False)(v2_xxreal_0 (k6_xcmplx_0 X2 X1)False)v1_xreal_0 X2v1_xreal_0 X1v3_xxreal_0 X1False)(∀X1 X2, (v3_xxreal_0 X2False)(v2_xxreal_0 (k2_xcmplx_0 X1 X2)False)v1_xreal_0 X2v1_xreal_0 X1v2_xxreal_0 X1False)(∀X1 X2, (v3_xxreal_0 X2False)(v2_xxreal_0 (k2_xcmplx_0 X2 X1)False)v1_xreal_0 X2v1_xreal_0 X1v2_xxreal_0 X1False)(∀X1 X2, (v3_xxreal_0 X2False)(v3_xxreal_0 (k6_xcmplx_0 X1 X2)False)v1_xreal_0 X2v1_xreal_0 X1v3_xxreal_0 X1False)(∀X2 X1, ((k2_nat_1 X1 X2) = (k2_xcmplx_0 X1 X2)False)v7_ordinal1 X2m1_subset_1 X1 k5_numbersFalse)(∀X2 X1, ((k2_nat_1 X1 X2) = (k2_nat_1 X2 X1)False)v7_ordinal1 X2m1_subset_1 X1 k5_numbersFalse)(∀X2 X1, ((k4_nat_1 X1 X2) = (k4_nat_1 X2 X1)False)v7_ordinal1 X2m1_subset_1 X1 k5_numbersFalse)(∀X2 X1, ((k4_nat_1 X1 X2) = (k3_xcmplx_0 X1 X2)False)v7_ordinal1 X2m1_subset_1 X1 k5_numbersFalse)(∀X1, (v1_abian X1False)v1_int_1 X1v1_abian (k2_xcmplx_0 X1 np__2)False)(∀X2 X1, ((k6_xcmplx_0 (k4_xcmplx_0 X1) (k4_xcmplx_0 X2)) = (k6_xcmplx_0 X2 X1)False)v1_xcmplx_0 X2v1_xcmplx_0 X1False)(∀X1 X2, (v1_abian X2False)(v1_abian X1False)(v1_abian (k6_xcmplx_0 X1 X2)False)v1_int_1 X2v1_int_1 X1False)(∀X1 X2, (v1_abian X2False)(v1_abian X1False)(v1_abian (k2_xcmplx_0 X1 X2)False)v1_int_1 X2v1_int_1 X1False)(∀X2 X1, (v1_abian (k3_xcmplx_0 X1 X2)False)v1_abian X1v1_int_1 X2v1_int_1 X1False)(∀X2 X1, (v1_abian (k3_xcmplx_0 X2 X1)False)v1_abian X1v1_int_1 X2v1_int_1 X1False)(∀X2 X1, (v1_xboole_0 X1False)(v3_xxreal_0 X1False)(v2_xxreal_0 X2False)v1_xreal_0 X2v1_xreal_0 X1r1_xxreal_0 X1 X2False)(∀X1 X2, (v1_xboole_0 X2False)(v3_xxreal_0 X1False)(v2_xxreal_0 X2False)v1_xreal_0 X2v1_xreal_0 X1r1_xxreal_0 X1 X2False)(∀X1 X2, (v2_xxreal_0 X2False)v1_xreal_0 X2v1_xreal_0 X1v2_xxreal_0 X1r1_xxreal_0 X1 X2False)(∀X1 X2, (v2_xxreal_0 X2False)v1_xreal_0 X2v1_xreal_0 X1v2_xxreal_0 X1r1_xxreal_0 X1 X2False)(∀X2 X1, (v3_xxreal_0 X1False)v1_xreal_0 X2v1_xreal_0 X1v3_xxreal_0 X2r1_xxreal_0 X1 X2False)(∀X2 X1, (v3_xxreal_0 X1False)v1_xreal_0 X2v1_xreal_0 X1v3_xxreal_0 X2r1_xxreal_0 X1 X2False)(∀X2 X1, ((k2_xcmplx_0 X1 (k4_xcmplx_0 X2)) = (k6_xcmplx_0 X1 X2)False)v1_xcmplx_0 X2v1_xcmplx_0 X1False)(∀X2 X1, ((k2_xcmplx_0 X1 (k4_xcmplx_0 X2)) = (k6_xcmplx_0 X1 X2)False)v1_xcmplx_0 X2v1_xcmplx_0 X1False)(∀X2 X1, (r1_tarski X1 X2False)m1_subset_1 X1 (k1_zfmisc_1 X2)False)(∀X2 X1, r2_hidden X2 X1r2_hidden X1 X2False)(∀X2 X1, (v7_ordinal1 (k2_xcmplx_0 X1 X2)False)v7_ordinal1 X2v7_ordinal1 X1False)(∀X2 X1, (v7_ordinal1 (k1_newton X1 X2)False)v7_ordinal1 X2v7_ordinal1 X1False)(∀X2 X1, (v7_ordinal1 (k3_xcmplx_0 X1 X2)False)v7_ordinal1 X2v7_ordinal1 X1False)(∀X2 X1, (v1_int_1 (k6_xcmplx_0 X1 X2)False)v1_int_1 X2v1_int_1 X1False)(∀X2 X1, (v1_int_1 (k2_xcmplx_0 X1 X2)False)v1_int_1 X2v1_int_1 X1False)(∀X2 X1, (v1_int_1 (k3_xcmplx_0 X1 X2)False)v1_int_1 X2v1_int_1 X1False)(∀X2 X1, (v1_rat_1 (k6_xcmplx_0 X1 X2)False)v1_rat_1 X2v1_rat_1 X1False)(∀X2 X1, (v1_rat_1 (k2_xcmplx_0 X1 X2)False)v1_rat_1 X2v1_rat_1 X1False)(∀X2 X1, (v1_rat_1 (k3_xcmplx_0 X1 X2)False)v1_rat_1 X2v1_rat_1 X1False)(∀X1 X2, (v1_xcmplx_0 (k1_newton X1 X2)False)v1_xcmplx_0 X1v7_ordinal1 X2False)(∀X2 X1, (v1_xreal_0 (k6_xcmplx_0 X1 X2)False)v1_xreal_0 X2v1_xreal_0 X1False)(∀X2 X1, (v1_xreal_0 (k2_prepower X1 X2)False)v1_xreal_0 X2v7_ordinal1 X1False)(∀X2 X1, (v1_xreal_0 (k2_xcmplx_0 X1 X2)False)v1_xreal_0 X2v1_xreal_0 X1False)(∀X1 X2, (v1_xreal_0 (k1_newton X1 X2)False)v1_xreal_0 X1v7_ordinal1 X2False)(∀X2 X1, (v1_xreal_0 (k3_xcmplx_0 X1 X2)False)v1_xreal_0 X2v1_xreal_0 X1False)(∀X2 X1, (v1_xreal_0 (k1_power X1 X2)False)v1_xreal_0 X2v7_ordinal1 X1False)(∀X1 X2, (v5_membered X2False)v5_membered X1m1_subset_1 X2 (k1_zfmisc_1 X1)False)(∀X1 X2, (v4_membered X2False)v4_membered X1m1_subset_1 X2 (k1_zfmisc_1 X1)False)(∀X1 X2, (v3_membered X2False)v3_membered X1m1_subset_1 X2 (k1_zfmisc_1 X1)False)(∀X1 X2, (v2_membered X2False)v2_membered X1m1_subset_1 X2 (k1_zfmisc_1 X1)False)(∀X1 X2, (v1_membered X2False)v1_membered X1m1_subset_1 X2 (k1_zfmisc_1 X1)False)(∀X1 X2, (v6_membered X2False)v6_membered X1m1_subset_1 X2 (k1_zfmisc_1 X1)False)(∀X2 X1, (r1_xxreal_0 X2 X1False)(r1_xxreal_0 X1 X2False)v1_xxreal_0 X2v1_xxreal_0 X1False)(∀X2 X1, (m1_subset_1 X1 (k1_zfmisc_1 X2)False)r1_tarski X1 X2False)(∀X2 X1, ((k2_xcmplx_0 X1 X2) = (k2_xcmplx_0 X2 X1)False)v1_xcmplx_0 X2v1_xcmplx_0 X1False)(∀X2 X1, ((k3_xcmplx_0 X1 X2) = (k3_xcmplx_0 X2 X1)False)v1_xcmplx_0 X2v1_xcmplx_0 X1False)(∀X1, (v1_abian (k2_xcmplx_0 X1 np__2)False)v1_abian X1v1_int_1 X1False)(∀X1 X2, (v1_xboole_0 X2False)(r2_hidden X1 X2False)m1_subset_1 X1 X2False)(∀X1, (v1_abian X1False)(v1_abian (k6_xcmplx_0 X1 np__1)False)v1_int_1 X1False)(∀X1, (v1_abian X1False)(v1_abian (k2_xcmplx_0 X1 np__1)False)v1_int_1 X1False)(∀X1 X2, (v3_xxreal_0 X2False)(v2_xxreal_0 X1False)(r1_xxreal_0 X1 X2False)v1_xreal_0 X2v1_xreal_0 X1False)(∀X1 X2, (v3_xxreal_0 X2False)(v2_xxreal_0 X1False)(r1_xxreal_0 X1 X2False)v1_xreal_0 X2v1_xreal_0 X1False)(∀X2 X1, (m1_subset_1 X1 X2False)r2_hidden X1 X2False)(∀X1, (v1_abian (k3_xcmplx_0 np__2 X1)False)v1_int_1 X1False)(∀X1 X2, (v7_ordinal1 X2False)v6_membered X1m1_subset_1 X2 X1False)(∀X1 X2, (v1_int_1 X2False)v5_membered X1m1_subset_1 X2 X1False)(∀X1 X2, (v1_rat_1 X2False)v4_membered X1m1_subset_1 X2 X1False)(∀X1 X2, (v1_xxreal_0 X2False)v2_membered X1m1_subset_1 X2 X1False)(∀X1 X2, (v1_xcmplx_0 X2False)v1_membered X1m1_subset_1 X2 X1False)(∀X1 X2, (v1_xreal_0 X2False)v3_membered X1m1_subset_1 X2 X1False)(∀X1, (v3_membered X1False)m1_subset_1 X1 (k1_zfmisc_1 k1_numbers)False)(∀X1, (v6_membered X1False)m1_subset_1 X1 (k1_zfmisc_1 k5_numbers)False)(∀X1, (v1_abian X1False)(m1_subset_1 (esk26_1 X1) k5_numbersFalse)v7_ordinal1 X1False)(∀X1 X2, v1_xboole_0 X2r2_hidden X1 X2False)(∀X2 X1, (r1_xxreal_0 X1 X1False)v1_xxreal_0 X2v1_xxreal_0 X1False)(∀X1, (v2_xxreal_0 X1False)v1_xreal_0 X1v3_xxreal_0 (k4_xcmplx_0 X1)False)(∀X1, (v3_xxreal_0 X1False)v1_xreal_0 X1v2_xxreal_0 (k4_xcmplx_0 X1)False)(∀X1, ((k3_xcmplx_0 X1 (k4_xcmplx_0 np__1)) = (k4_xcmplx_0 X1)False)v1_xcmplx_0 X1False)(∀X1, v3_xxreal_0 X1m1_subset_1 X1 k5_numbersFalse)(∀X1, (v6_membered X1False)m1_subset_1 X1 k5_numbersFalse)(∀X1, (v1_xreal_0 X1False)m1_subset_1 X1 k1_numbersFalse)(∀X1, (v2_xxreal_0 X1False)(v1_xcmplx_0 (k4_xcmplx_0 X1)False)v1_xreal_0 X1False)(∀X1, (v3_xxreal_0 X1False)(v1_xcmplx_0 (k4_xcmplx_0 X1)False)v1_xreal_0 X1False)(∀X1, v1_xxreal_0 X1v3_xxreal_0 X1v2_xxreal_0 X1False)(∀X1, v1_xxreal_0 X1v3_xxreal_0 X1v2_xxreal_0 X1False)(∀X1, v1_xxreal_0 X1v1_xboole_0 X1v2_xxreal_0 X1False)(∀X1, v1_xxreal_0 X1v1_xboole_0 X1v2_xxreal_0 X1False)(∀X1, v1_xxreal_0 X1v1_xboole_0 X1v3_xxreal_0 X1False)(∀X1, v1_xxreal_0 X1v1_xboole_0 X1v3_xxreal_0 X1False)(∀X1, (v1_xboole_0 X1False)v2_setfam_1 (k1_zfmisc_1 X1)False)(∀X1, (v1_xboole_0 X1False)(v3_xxreal_0 X1False)(v2_xxreal_0 X1False)v1_xxreal_0 X1False)(∀X1, (v1_xboole_0 X1False)(v3_xxreal_0 X1False)(v2_xxreal_0 X1False)v1_xxreal_0 X1False)(∀X1, (v1_xboole_0 X1False)(v3_xxreal_0 X1False)(v2_xxreal_0 X1False)v1_xxreal_0 X1False)(∀X1, ((k3_xcmplx_0 np__1 X1) = X1False)v1_xcmplx_0 X1False)(∀X1, ((k6_xcmplx_0 X1 k6_numbers) = X1False)v1_xcmplx_0 X1False)(∀X1, ((k2_xcmplx_0 X1 k6_numbers) = X1False)v1_xcmplx_0 X1False)(∀X1, ((k3_xcmplx_0 X1 k6_numbers) = k6_numbersFalse)v1_xcmplx_0 X1False)(∀X1, (v1_abian X1False)v1_int_1 X1v1_xboole_0 X1False)(∀X1, ((k4_xcmplx_0 (k4_xcmplx_0 X1)) = X1False)v1_xcmplx_0 X1False)(∀X1, (v1_int_1 (k4_xcmplx_0 X1)False)v1_int_1 X1False)(∀X1, (v1_rat_1 (k4_xcmplx_0 X1)False)v1_rat_1 X1False)(∀X1, (v1_xcmplx_0 (k4_xcmplx_0 X1)False)v1_int_1 X1False)(∀X1, (v1_xcmplx_0 (k4_xcmplx_0 X1)False)v1_rat_1 X1False)(∀X1, (v1_xcmplx_0 (k4_xcmplx_0 X1)False)v1_xcmplx_0 X1False)(∀X1, (v1_xcmplx_0 (k4_xcmplx_0 X1)False)v1_xreal_0 X1False)(∀X1, (v1_xreal_0 (k4_xcmplx_0 X1)False)v1_xreal_0 X1False)(∀X2 X1, (X1 = X2False)v1_xboole_0 X2v1_xboole_0 X1False)((r1_xxreal_0 np__1 esk3_0False)v1_abian esk3_0False)((r1_xxreal_0 np__1 esk3_0False)v1_abian esk2_0False)((r1_xxreal_0 np__1 esk2_0False)v1_abian esk3_0False)((r1_xxreal_0 np__1 esk2_0False)v1_abian esk2_0False)((r1_xxreal_0 k6_numbers esk1_0False)v1_abian esk3_0False)((r1_xxreal_0 k6_numbers esk1_0False)v1_abian esk2_0False)(∀X1, v7_ordinal1 X1v3_xxreal_0 X1False)(∀X1, (v7_membered X1False)v1_xboole_0 X1False)(∀X1, (v3_ordinal1 X1False)v7_ordinal1 X1False)(∀X1, (v1_zfmisc_1 X1False)v2_setfam_1 X1False)(∀X1, (v1_int_1 X1False)v7_ordinal1 X1False)(∀X1, (v5_membered X1False)v6_membered X1False)(∀X1, (v1_rat_1 X1False)v1_int_1 X1False)(∀X1, (v4_membered X1False)v5_membered X1False)(∀X1, (v3_membered X1False)v4_membered X1False)(∀X1, (v1_xxreal_0 X1False)v7_ordinal1 X1False)(∀X1, (v1_xxreal_0 X1False)v1_xreal_0 X1False)(∀X1, (v2_membered X1False)v3_membered X1False)(∀X1, (v1_xcmplx_0 X1False)v1_xreal_0 X1False)(∀X1, (v1_membered X1False)v3_membered X1False)(∀X1, (v6_membered X1False)v1_xboole_0 X1False)(∀X1, (v1_xreal_0 X1False)v7_ordinal1 X1False)(∀X1, (v1_xreal_0 X1False)v1_int_1 X1False)(∀X1, (v1_xreal_0 X1False)v1_rat_1 X1False)(∀X1, (X1 = k1_xboole_0False)v1_xboole_0 X1False)((k1_power (k4_nat_1 esk2_0 esk3_0) (k1_newton esk1_0 (k2_nat_1 esk2_0 esk3_0))) = (k3_xcmplx_0 (k1_power esk2_0 esk1_0) (k1_power esk3_0 esk1_0))False)(r1_xxreal_0 np__0 (k4_xcmplx_0 np__1)False)(r1_xxreal_0 np__2 (k4_xcmplx_0 np__1)False)(r1_xxreal_0 np__1 (k4_xcmplx_0 np__1)False)(r1_xxreal_0 np__2 np__0False)(r1_xxreal_0 np__2 np__1False)(r1_xxreal_0 np__1 np__0False)(v1_finset_1 k1_numbersFalse)(v1_xboole_0 esk20_0False)(v1_xboole_0 esk16_0False)(v1_xboole_0 esk14_0False)(v1_xboole_0 esk13_0False)(v1_xboole_0 esk7_0False)(v1_xboole_0 np__2False)(v1_xboole_0 k1_numbersFalse)(v1_xboole_0 np__1False)(v1_abian esk23_0False)((m2_subset_1 np__0 k1_numbers k5_numbersFalse)False)((m2_subset_1 np__2 k1_numbers k5_numbersFalse)False)((m2_subset_1 np__1 k1_numbers k5_numbersFalse)False)((m2_subset_1 k6_numbers k1_numbers k5_numbersFalse)False)(((k6_xcmplx_0 (k4_xcmplx_0 np__2) (k4_xcmplx_0 np__1)) = (k4_xcmplx_0 np__1)False)False)(((k2_xcmplx_0 (k4_xcmplx_0 np__1) (k4_xcmplx_0 np__1)) = (k4_xcmplx_0 np__2)False)False)((r1_xxreal_0 (k4_xcmplx_0 np__1) (k4_xcmplx_0 np__1)False)False)(((k6_xcmplx_0 (k4_xcmplx_0 np__2) (k4_xcmplx_0 np__2)) = np__0False)False)(((k6_xcmplx_0 (k4_xcmplx_0 np__1) (k4_xcmplx_0 np__2)) = np__1False)False)(((k6_xcmplx_0 (k4_xcmplx_0 np__1) (k4_xcmplx_0 np__1)) = np__0False)False)(∀X1, (m1_subset_1 (esk4_1 X1) X1False)False)(((k6_xcmplx_0 (k4_xcmplx_0 np__1) np__0) = (k4_xcmplx_0 np__1)False)False)(((k6_xcmplx_0 (k4_xcmplx_0 np__1) np__1) = (k4_xcmplx_0 np__2)False)False)(((k2_xcmplx_0 (k4_xcmplx_0 np__1) np__0) = (k4_xcmplx_0 np__1)False)False)(((k3_xcmplx_0 (k4_xcmplx_0 np__2) np__1) = (k4_xcmplx_0 np__2)False)False)(((k2_xcmplx_0 np__0 (k4_xcmplx_0 np__1)) = (k4_xcmplx_0 np__1)False)False)(((k2_xcmplx_0 np__1 (k4_xcmplx_0 np__2)) = (k4_xcmplx_0 np__1)False)False)(((k3_xcmplx_0 np__1 (k4_xcmplx_0 np__2)) = (k4_xcmplx_0 np__2)False)False)((r1_xxreal_0 (k4_xcmplx_0 np__1) np__0False)False)((r1_xxreal_0 (k4_xcmplx_0 np__1) np__2False)False)((r1_xxreal_0 (k4_xcmplx_0 np__1) np__1False)False)((m1_subset_1 esk14_0 (k1_zfmisc_1 k1_numbers)False)False)((m1_subset_1 k5_numbers (k1_zfmisc_1 k1_numbers)False)False)(((k2_xcmplx_0 (k4_xcmplx_0 np__2) np__2) = np__0False)False)(((k2_xcmplx_0 (k4_xcmplx_0 np__1) np__2) = np__1False)False)(((k2_xcmplx_0 (k4_xcmplx_0 np__1) np__1) = np__0False)False)(((k6_xcmplx_0 np__0 (k4_xcmplx_0 np__1)) = np__1False)False)(((k6_xcmplx_0 np__1 (k4_xcmplx_0 np__1)) = np__2False)False)(((k2_xcmplx_0 np__2 (k4_xcmplx_0 np__1)) = np__1False)False)(((k2_xcmplx_0 np__1 (k4_xcmplx_0 np__1)) = np__0False)False)(∀X1, (r1_tarski X1 X1False)False)(((k6_xcmplx_0 np__0 np__2) = (k4_xcmplx_0 np__2)False)False)(((k6_xcmplx_0 np__0 np__1) = (k4_xcmplx_0 np__1)False)False)(((k6_xcmplx_0 np__1 np__2) = (k4_xcmplx_0 np__1)False)False)((r1_xxreal_0 np__0 np__0False)False)((r1_xxreal_0 np__0 np__2False)False)((r1_xxreal_0 np__0 np__1False)False)((r1_xxreal_0 np__2 np__2False)False)((r1_xxreal_0 np__1 np__2False)False)((r1_xxreal_0 np__1 np__1False)False)((m1_subset_1 esk8_0 k1_numbersFalse)False)((m1_subset_1 esk6_0 k1_numbersFalse)False)((m1_subset_1 esk3_0 k5_numbersFalse)False)((m1_subset_1 esk2_0 k5_numbersFalse)False)((m1_subset_1 np__0 k1_numbersFalse)False)((m1_subset_1 np__0 k5_numbersFalse)False)((m1_subset_1 k1_xboole_0 k4_ordinal1False)False)((m1_subset_1 np__2 k1_numbersFalse)False)((m1_subset_1 np__2 k5_numbersFalse)False)((m1_subset_1 np__1 k1_numbersFalse)False)((m1_subset_1 np__1 k5_numbersFalse)False)(((k6_xcmplx_0 np__2 np__0) = np__2False)False)(((k6_xcmplx_0 np__2 np__2) = np__0False)False)(((k6_xcmplx_0 np__2 np__1) = np__1False)False)(((k6_xcmplx_0 np__1 np__0) = np__1False)False)(((k6_xcmplx_0 np__1 np__1) = np__0False)False)(((k2_xcmplx_0 np__0 np__0) = np__0False)False)(((k2_xcmplx_0 np__0 np__2) = np__2False)False)(((k2_xcmplx_0 np__0 np__1) = np__1False)False)(((k2_xcmplx_0 np__2 np__0) = np__2False)False)(((k2_xcmplx_0 np__1 np__0) = np__1False)False)(((k2_xcmplx_0 np__1 np__1) = np__2False)False)(((k3_xcmplx_0 np__0 np__0) = np__0False)False)(((k3_xcmplx_0 np__0 np__2) = np__0False)False)(((k3_xcmplx_0 np__0 np__1) = np__0False)False)(((k3_xcmplx_0 np__2 np__0) = np__0False)False)(((k3_xcmplx_0 np__2 np__1) = np__2False)False)(((k3_xcmplx_0 np__1 np__0) = np__0False)False)(((k3_xcmplx_0 np__1 np__2) = np__2False)False)(((k3_xcmplx_0 np__1 np__1) = np__1False)False)(((k4_xcmplx_0 (k4_xcmplx_0 np__2)) = np__2False)False)(((k4_xcmplx_0 (k4_xcmplx_0 np__1)) = np__1False)False)((v2_xxreal_0 esk18_0False)False)((v2_xxreal_0 esk17_0False)False)((v2_xxreal_0 np__2False)False)((v2_xxreal_0 np__1False)False)((v3_xxreal_0 esk22_0False)False)((v3_xxreal_0 esk21_0False)False)((v7_membered esk20_0False)False)((v7_membered k4_ordinal1False)False)((v7_membered k1_numbersFalse)False)((v3_ordinal1 esk14_0False)False)((v1_xboole_0 esk25_0False)False)((v1_xboole_0 esk24_0False)False)((v1_xboole_0 esk9_0False)False)((v1_xboole_0 np__0False)False)((v1_xboole_0 k1_xboole_0False)False)((v1_int_1 esk23_0False)False)((v1_int_1 esk19_0False)False)((v1_int_1 esk12_0False)False)((v1_int_1 esk6_0False)False)((v1_rat_1 esk15_0False)False)((v1_rat_1 esk8_0False)False)((v3_membered k1_numbersFalse)False)((v1_xxreal_0 esk25_0False)False)((v1_xxreal_0 esk24_0False)False)((v1_xxreal_0 esk23_0False)False)((v1_xxreal_0 esk22_0False)False)((v1_xxreal_0 esk21_0False)False)((v1_xxreal_0 esk19_0False)False)((v1_xxreal_0 esk18_0False)False)((v1_xxreal_0 esk17_0False)False)((v1_xxreal_0 esk11_0False)False)((v1_xxreal_0 esk8_0False)False)((v1_xxreal_0 esk6_0False)False)((v1_xcmplx_0 esk24_0False)False)((v1_xcmplx_0 esk23_0False)False)((v1_xcmplx_0 esk21_0False)False)((v1_xcmplx_0 esk19_0False)False)((v1_xcmplx_0 esk17_0False)False)((v1_xcmplx_0 esk8_0False)False)((v1_xcmplx_0 esk6_0False)False)((v6_membered esk20_0False)False)((v6_membered esk13_0False)False)((v6_membered esk7_0False)False)((v6_membered k4_ordinal1False)False)((v1_abian esk19_0False)False)((v1_xreal_0 esk24_0False)False)((v1_xreal_0 esk23_0False)False)((v1_xreal_0 esk21_0False)False)((v1_xreal_0 esk19_0False)False)((v1_xreal_0 esk17_0False)False)((v1_xreal_0 esk10_0False)False)((v1_xreal_0 esk8_0False)False)((v1_xreal_0 esk6_0False)False)((v1_xreal_0 esk1_0False)False)(((k4_xcmplx_0 np__0) = np__0False)False)((k5_numbers = k4_ordinal1False)False)((k1_xboole_0 = k6_numbersFalse)False)False
Proof:
The rest of the proof is missing.